Code: BIE-JPO Computer Units
Lecturer: Ing. Pavel Kubalík Ph.D. Weekly load: 2P+2C Completion: A, EX
Department: 18103 Credits: 5 Semester: W
Description:
Students know the internal structure and organization of computer or processor components and their interfacing with the environment. They understand the organization of main memory and other internal memories (addressable, LIFO, FIFO and CAM). They know the organization of an arithmetic unit. They learn the design methodology for control units and controllers, as well as basic principles of communication with peripheral devices and buses. They understand the architecture of a bus system.
Contents:
1. Organization and structure of von Neumann computers.
2. Binary adders, subtractors, and shifters.
3. Arithmetic and logic unit of a simple processor.
4. Control unit and controllers; microprogrammed control unit.
5. Wired control unit.
6. Binary multiplication and division and their implementation.
7. Floating point representation.
8. Basic principles of error detection and correction.
9. Linear and cyclic codes.
10. Main memory - possible organizations and interfaces.
11. Other internal memories, their organization and use - addressable memories, LIFO, FIFO, CAM.
12. I/O units and their control - DMA, channels and I/O processors.
13. Buses - types, modes, arbitration.
Seminar contents:
1. Number systems, conversions and operations.
2. Representations of negative numbers.
3. Simple processor - instructions, machine code, data part.
4. Simple processor - instruction cycle, interface.
5. Simple processor - microprogramming.
6. Simple processor - demonstration of a microprogram.
7. Wired controller design.
8. Multipliers and dividers.
9. Floating point representation.
10. [2] Design of a processor component on FPGA.
11. Demonstration of the designed processor component.
12. Error detection codes.
Recommended literature:
1. Hennesy, J. L., Patterson, D. A. ''Computer Architecture: A Quantitative Approach, Third Edition''. Morgan Kaufmann, 2002. ISBN 1558605967.
2. Tanenbaum, A. S. ''Structured Computer Organization (5th Edition)''. Prentice Hall, 2005. ISBN 0131485210.
3. Stallings, W. ''Computer Organization and Architecture: Designing for Performance (7th Edition)''. Prentice Hall, 2005. ISBN 0131856448.
4. Hamacher, C., Vranesic, Z., Zaky, S. ''Computer Organization''. McGraw-Hill, 2001. ISBN 0072320869.
Keywords:
Computer, computer organization, computer architecture, arithmetic and logic unit, control unit, memory, error control codes, input/output, buses.

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